The present invention relates to the decoding of serial digital signals, and more particularly to the digital decoding of biphase-mark encoded serial digital signals.
An internationally recognized standard for transmitting a digitized audio signal is known as AES-3 1992. Under this standard the digital audio signal is serialized and then encoded to form a polarity-free signal. This encoding, known as biphase-mark, encodes the digital audio signal so that each bit has a transition to the opposite polarity at the end of each bit interval. Logical "ones" have an additional transition in the middle of the bit interval. Decoding of this encoded audio signal requires extracting a clock signal from the encoded audio signal as well as extracting the sequence of logical "ones" and "zeros" that represent the signal content.
Prior decoders, such as the CS8411 manufactured by Crystal Semiconductor Corporation of Austin, Tex., U.S. of America, use an analog decoding technique. The serial digital audio signal is input to the decoder, which includes an analog phase-locked loop, to recover the clock that is used to decode the signal. These decoders are expensive and susceptible to jitter so that they do not always decode properly when the transitions in the signal do not always occur at the precise expected time.
Thus a method of decoding biphase-mark encoded serial digital signals is desired that is less expensive and less susceptible to jitter than prior decoders.